Semiconductor memory chips are widely used in many fields such as industrial control and consuming electronics. High integration density, low power consumption, and high speed are essential properties of these memory chips. To enhance the storage capability of a memory chip in the same die area, generally there are two methods. One method is to scale down the feature size of the semiconductor memory cell. The second method is to get a better design by improving the architecture or applying novel devices. Due to the MOSFET-based structure in the electrically erasable programmable read only memory (EEPROM) and nitride read only memory (NROM), the short channel effects of MOSFET become handicaps as the feature size is scaled down in these memory cells. Therefore, a novel device structure with suppressed short channel effects is preferred. According to this requirement, a self-aligned vertical Tunneling-Field-Effect-Transistor Read only memory (TROM) is proposed in the present invention. Because of the suppressed short channel effects in a Tunneling-Field-Effect-Transistor (TFET) structure, the TROM can be scaled down to 20 nm gate length and the leakage current remains low.
The density of a memory chip can be improved by using a better design. An example is the application of NROM. The NROM has 2-bit storage in one memory cell. Therefore, the NROM has a higher storage density than that of EEPROM. Similar to NROM, the presently invented self-aligned vertical TROM cell has the 2-bit storage capability. The density of the vertical TROM will be higher than that of EEPROM.
The memory cells array is generally arranged in a matrix layout to realize the mass storage. There are two architectures in the EEPROM flash memory matrix. One architecture is the NAND architecture and the other is the NOR architecture, Using the NAND architecture, the memory density is higher than that of NOR architecture because that the source and drain contact pads are not necessary in the NAND architecture. Because of the self-aligned vertical structure of a memory cell, a new architecture that applies both the NOR architecture and the NAND architecture becomes possible in the present invention. The advantages of both NAND and NOR architectures are realized in the combined architecture.